CVE-2026-80562 Affecting linux-6.12 package, versions <6.12.107-1~deb12u1


Severity

Recommended
low

Based on default assessment until relevant scores are available.

Threat Intelligence

EPSS
0.18% (8th percentile)

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  • Snyk IDSNYK-ECHOLATEST-LINUX612-19964389
  • published20 Sept 2026
  • disclosed26 Aug 2026

Introduced: 26 Aug 2026

NewCVE-2026-80562  (opens in a new tab)

How to fix?

Upgrade Echo:latest linux-6.12 to version 6.12.107-1~deb12u1 or higher.

NVD Description

Note: Versions mentioned in the description apply only to the upstream linux-6.12 package and not the linux-6.12 package as distributed by Echo. See How to fix? for Echo:latest relevant fixed versions and status.

In the Linux kernel, the following vulnerability has been resolved:

gpio: ml-ioh: use raw_spinlock_t for the register lock

ioh_irq_type() is registered as the irq_chip .irq_set_type callback and takes chip->spinlock with spin_lock_irqsave(). This callback is reached from __setup_irq() -> __irq_set_trigger() -> chip->irq_set_type() while the caller holds desc->lock, a raw_spinlock_t, with hardirqs disabled. That context is not sleepable, but on PREEMPT_RT a regular spinlock_t is an rtmutex-backed sleeping lock, so acquiring it there is invalid. ioh_irq_enable() and ioh_irq_disable() take the same lock from the .irq_enable/.irq_disable callbacks, which are likewise invoked with desc->lock held.

Convert the register lock to raw_spinlock_t. The same lock also serializes the GPIO direction/value callbacks and the suspend/resume register save/restore, and those critical sections only perform short sequences of MMIO register accesses (ioread32()/iowrite32()); the .irq_set_type callback additionally emits a dev_warn() on an unsupported type. None of these are sleepable operations, so keeping this register lock non-sleeping is appropriate for the irqchip callbacks and does not change the GPIO-side locking contract.

This is the same fix as commit a02b8950d619 ("gpio: pch: use raw_spinlock_t for the register lock"); this driver shares the same structure as gpio-pch.

CVSS Base Scores

version 3.1