Improper Handling of Exceptional Conditions Affecting xen package, versions <4.14.0-r1


Severity

Recommended
0.0
medium
0
10

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Threat Intelligence

EPSS
0.05% (16th percentile)

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  • Snyk IDSNYK-ALPINE316-XEN-2845085
  • published24 Sept 2020
  • disclosed23 Sept 2020

Introduced: 23 Sep 2020

CVE-2020-25602  (opens in a new tab)
CWE-755  (opens in a new tab)

How to fix?

Upgrade Alpine:3.16 xen to version 4.14.0-r1 or higher.

NVD Description

Note: Versions mentioned in the description apply only to the upstream xen package and not the xen package as distributed by Alpine. See How to fix? for Alpine:3.16 relevant fixed versions and status.

An issue was discovered in Xen through 4.14.x. An x86 PV guest can trigger a host OS crash when handling guest access to MSR_MISC_ENABLE. When a guest accesses certain Model Specific Registers, Xen first reads the value from hardware to use as the basis for auditing the guest access. For the MISC_ENABLE MSR, which is an Intel specific MSR, this MSR read is performed without error handling for a #GP fault, which is the consequence of trying to read this MSR on non-Intel hardware. A buggy or malicious PV guest administrator can crash Xen, resulting in a host Denial of Service. Only x86 systems are vulnerable. ARM systems are not vulnerable. Only Xen versions 4.11 and onwards are vulnerable. 4.10 and earlier are not vulnerable. Only x86 systems that do not implement the MISC_ENABLE MSR (0x1a0) are vulnerable. AMD and Hygon systems do not implement this MSR and are vulnerable. Intel systems do implement this MSR and are not vulnerable. Other manufacturers have not been checked. Only x86 PV guests can exploit the vulnerability. x86 HVM/PVH guests cannot exploit the vulnerability.

CVSS Scores

version 3.1